Integrated circuit devices typically include a semiconductor die or chip that is assembled in a package. A package typically has a substrate portion that the chip is electrically connected to. Usually the substrate is larger than the chip and has a larger array of leads or electrical contact points than that of the chip to allow for ease of assembly of the packaged chip onto a circuit board. One such package configuration is a flip-chip package.
An example of a conventional flip-chip package 20 is shown in FIG. 1. In this example, the chip 22 is electrically connected to the substrate 24 by an array of solder bumps 26. The substrate 24 in this example has an array of solder balls 28 (i.e., ball grid array or BGA), which may be used to attach the packaged chip 20 to a circuit board (not shown), for example. Typically, an underfill material 30 is fed into the free space or gap between the chip 22 and the substrate 24 after the chip 22 is electrically connected to the substrate 24 via the solder bumps 26. Because the distance between the chip 22 and the substrate 24 is often very small (e.g., between about 30 μm and about 50 μm), the underfill material 30 may be fed into the gap between the chip 22 and the substrate 24 by capillary action. After the underfill material 30 is placed between the chip 22 and the substrate 24, as shown in FIG. 1, the underfill material 30 is often cured. Such curing may include heating the package 20 up to a temperature of about 150° C., for example.
At some point after the chip 22 is electrically connected to the substrate 24 and the underfill material 30 is placed and cured, a lid 32 is typically placed over the chip 22. The lid 32 is shown in phantom lines in FIG. 1 for purposes of illustration. In addition to protecting the chip 22 in the package 20, this lid 32 may be made from aluminum and act as a heat sink to provide better cooling for the chip 22, for example.
One of the purposes of the underfill material 30 is to more evenly distribute the stresses between the chip 22 and the substrate 24 to reduce the stresses experienced by the solder bumps 26, solder bump joints, and/or circuitry layers above/below solder joints. Such stresses are caused, at least in part, by different coefficients of thermal expansion between the chip 22, the solder bumps 26, and the substrate 24 (i.e., coefficient of thermal expansion mismatch). The chip 22 is typically made from a silicon wafer, the substrate 24 is typically made from organic material having copper lines and vias extending therein, and the solder bumps 26 are typically made from a metal compound having a low melting point, for example. Thus, temperature changes (e.g., during use of the chip 22) cause stress on the solder bumps 26 connecting the chip 22 to the substrate 24 due to the different rates of material expansion/contraction between the chip 22 and the substrate 24 as the temperature changes. The underfill material 30 may also act as an adhesive to help retain the chip 22 to the substrate 24 so that not just the solder bumps 26 are holding the chip 22 in place. This further reduces stress exerted on the solder bumps 26.
When the underfill material 30 is cured, it is preferable that there are no voids or air pockets remaining between the chip 22 and the substrate 24 and/or within the underfill material 30. Such voids create points of stress concentration and may act as crack initiation sites. Once a crack initiates, it will often grow and propagate through the underfill material 30 until the stress is relieved. A crack may propagate into the chip itself and/or through a solder bump or some other line in the chip or substrate. This may cause a failure site or an open connection, either of which is highly undesirable and may cause the chip to function improperly or fail to function at all. Also, if a void happens to be located between two solder bumps, the material from those solder bumps may eventually extrude into the void causing a short between those bumps. This is also highly undesirable. Thus, one of the main goals in dispensing an underfill material 30 is to avoid the formation of voids or air pockets therein.
FIG. 2 shows a top view (chip side) of the substrate 24 without the chip 22 electrically connected thereto. In FIG. 2, the contacts 34 where the solder bumps will connect the chip to the substrate are shown to illustrate an example contact pattern. There are many possible variations for contact patterns. The contact pattern on the substrate 24 is typically the mirror image of the contact pattern on the chip 22. The solder bumps 26 may be formed on the substrate contacts 34 and/or the chip contacts. Hence, the pattern of the solder bumps 26 is usually the same as the contact pattern on the substrate 24 and/or the contact pattern on the chip 22.
FIG. 3 shows the substrate 24 of FIG. 2 with a chip 22 electrically connected thereto via solder bumps 26. The solder bumps 26 are shown with dashed lines in FIG. 3, as they are located between the chip 22 and the substrate 24 (see e.g., FIG. 1).
FIG. 4 illustrates the flow of underfill material 30 as it is drawn between the chip 22 and the substrate 24 of FIG. 3. In a conventional process, the underfill material 30 is typically dispensed at one end of the chip 22 and capillary action draws the underfill material 30 into the gap between the chip 22 and the substrate 24. Generally, the underfill material 30 is distributed faster or the capillary force is stronger in areas where the solder bumps 26 are located because the solder bumps 26 provide more surface area for the fluid (i.e., the underfill material 30) to grab onto. Hence, as illustrated in FIG. 4, the areas with higher densities of solder bumps 26 may be filled with underfill material 30 faster than other areas having lower solder bump density.
In FIG. 4, numerous phantom-lined outlines are shown to illustrate the progression of the underfill material 30 as it is drawn into the gap. A first phantom-lined outline 36 in FIG. 4 illustrates the area where the underfill material is initially dispensed. Note that by the fourth phantom-lined outline 38, the distribution of the underfill material is beginning to be uneven, as the underfill material is distributed faster at the outer edges where the solder bumps are located. By the sixth phantom-lined outline 40, the distribution of the underfill material is even more uneven. At the tenth phantom-lined outline 42, the underfill material has reached the other end of the chip 22 on the outer edges where the solder bumps 26 are more densely distributed. At the eleventh phantom-lined outline 44, the underfill material is beginning to be distributed along the end of the chip 22. Meanwhile at the central region of the chip 22, the underfill material is being distributed slower and has not reached the end rows of solder bumps 26. At the twelfth phantom-lined outline 46, the underfill material coming from the outer edges has met near the middle and formed an air pocket or air bubble 50, which remains trapped between the chip 22 and the substrate 24 within the underfill material 30. As discussed above, such air pockets or voids are highly undesirable. Hence, there is a need for a way to ensure that the underfill material gets distributed more evenly and preferably without voids or air pockets.